Recent years have seen increasingly higher performance in electronic devices such as portable information devices and information appliances, following the development of digital technology. As such, there is an increased demand for increasing capacity, reducing writing power consumption, accelerating speed during writing and reading, and extending operational life, in nonvolatile semiconductor memory devices.
In view of these demands, there has been an advance in the miniaturization of flash memories using existing floating gates.
Since a nonvolatile semiconductor storage device (resistance-change memory, hereinafter referred to as “ReRAM”) including, as a storage unit, a variable resistance element in which a resistance value stably held changes with application of a voltage pulse has a simple structure of memory cells, the miniaturization, the higher speed, and the lower power consumption are further expected.
For example, PTL 1 discloses a cross-point ReRAM intended for the miniaturization and the larger capacity, as a ReRAM.
In the ReRAM disclosed in PTL 1, striped lower electrodes are formed on a substrate, and an active layer is entirely formed over the lower electrodes. The active layer used is a variable resistance layer in which a resistance value reversibly changes with application of an electrical pulse. Striped upper electrodes are formed on the active layer so as to cross the lower electrodes.
In the ReRAM with such a structure, a region in which the lower electrodes cross the upper electrodes across the variable resistance layer functions as a storage unit, and each of the lower electrodes and the upper electrodes function as one of word lines and bit lines. The capacity can be increased using a cross-point ReRAM having such a structure.
However, the cross-point ReRAM has a problem in the influence of variable resistance layers in other rows and columns when a resistance value of a variable resistance layer formed at a cross-point at which the upper electrode and the lower electrode cross is read.
Here, a diode is inserted in series with the variable resistance layer in order to prevent the influence of variable resistance layers in the other rows and columns (see, for example, PTL 2).
PTL 2 discloses a ReRAM including: a substrate; a plurality of bit lines (lower electrodes) arranged in parallel with each other on the substrate; a plurality of word lines (upper electrodes) arranged in parallel with each other in a direction in which the word lines cross the bit lines; a resistor structure formed on each of the bit lines at a cross-point between the bit line and the word line; and a diode structure formed on each of the resistor structures so as to be in contact with the resistor structure and the word line.
As such, when a resistance value of a variable resistance layer is read, it is possible to solve the problem of the influence of variable resistance layers in the other rows and columns by changing the unit cell structure into a continuous stacked structure with one diode structure and one resistor structure.